To implement various functions on one chip, a recent CMIS semiconductor integrated circuit (hereinafter referred to as an LSI) is composed of more than several tens of millions of MIS transistors integrated therein. Like other products, the LSI also has a lifetime so that, after operating for a given post-manufacturing period, it may incur a failure or faulty operation. As major factors which cause the failure or faulty operation of the LSI, there have been known degradation of transistor properties resulting from a hot carrier degradation phenomenon or a bias temperature instability phenomenon, a broken line or a short circuit resulting from electromigration, and the like.
Because transistors composing an LSI have been miniaturized rapidly with the recent advances in manufacturing technology, a high electric field formed in the vicinity of the drain of each MIS transistor causes impact ionization of carriers so that hot carriers having high energy are more likely to be generated. The hot carriers may eventually result in faulty operation of the LSI since such carriers damage a gate oxide film, vary (degrade) the threshold voltage and drain current of a transistor with the passage of time, and resultantly change the property of operating frequency of the LSI composed of a group of transistors. To prevent this, measures should be taken by performing proper reliability evaluation against the hot carriers in the manufacturing process for the LSI or allowing for a design margin for ensuring reliability in accordance with a desired product lifetime in the design of the LSI.
FIG. 8 is a flow chart illustrating a typical process flow from the development of a device to the mass production thereof. First, process development is performed in Step ST101. Then, device evaluation is performed in Step ST102 and LSI design is performed in Step ST103, while it is judged in Step ST104 whether or not the device has any reliability problem. The process is improved till it is judged in Step ST104 that the device has no more reliability problem. On the other hand, it is judged in Step ST105 whether or not the LSI design performed in Step ST103 has any problem. The process flow moves to Step ST106 of LSI mass production if the device is judged to have no more reliability problem and if the LSI design is judged to have no more problem judgment process in Step ST105).
As shown in FIG. 9, an LSI can typically be decomposed into basic units, signal path 130, each composed of flip-flops 131 and circuits 132 which are disposed in several stages (N stages in FIG. 9) between the flip-flops 131. Each of the circuits 132 is mostly composed of logic circuits and a wiring providing a connection therebetween. A signal propagating through the series of circuits in each of signal paths is required to have a delay falling within a specified period determined by the cycle time of a clock signal 133 (which is mostly an inverse number of the operating frequency or clock frequency). The resulting relation is given by the following expression (1):t cycle≧Σti+K i=1 to N  (1)where t cycle is the cycle time as a design objective property, Σ ti is the total sum of signal propagation delays between the respective input and output terminals of the circuits i between the flip-flops, i.e., a signal path delay before degradation, and K is the sum of set-up times for the flip-flops 131 and the skews of the clock signal 133.
The signal path delay is not constant relative to the operating time of the LSI and varies due to hot carrier degradation as shown in the following expression (2):
 t cycle≧Σ[ti+Δti]+K i=1 to N  (2)
where Σ Δti is a variation in signal path delay due to degradation. The variation in delay due to the hot carrier degradation normally increases with the passage of time, though it differs depending on the types of circuits and operating conditions for each of the circuits including power-supply voltage, temperature, the number of times of operations, the slope of input signals, the direction of signal transition (rising or falling), output signal load, and manufacturing fluctuation. If consideration is thus given even to time-varying degradation, the right side of the expression (2) should fall within the cycle time.
To ensure the product lifetime of an LSI, it is necessary to design the LSI by preliminarily considering the influence of increased delay due to degradation and check whether or not a problem arises under the influence in evaluating the reliability of the LSI after manufacturing.
For conventional reliability evaluation, a ring oscillator circuit composed of a plurality of inverters 41 connected in a loop configuration to oscillate, such as the one shown in FIG. 10, has been used frequently. FIG. 11 shows the relationship between the operation time of the circuit and the degree of delay degradation. As shown in FIG. 11, the amount of delay degradation increases with the operating time. Reliability evaluation is performed by judging whether or not the degree G of delay degradation at the end of a lifetime T (e.g., ten years) to be guaranteed is equal to or less than a permissible value. The degree G of delay degradation also serves as a minimum time-varying degradation margin to be allowed for in LSI design. Since the degree of degradation can be determined by the reliability evaluating process (Step ST102) in FIG. 8, data on an amount of time-varying degradation margin (which will be described later) is transmitted to the LSI design (Step ST103).
In general, if a margin provided in designing an LSI, i.e., a design margin is excessively large, it guarantees excessively high reliability to the LSI. The reliability and performance of the LSI are generally in trade-off relation so that excessively high reliability imparted to the LSI eventually reduces the performance (e.g., operating frequency) of the LSI. If the design margin is excessively small, reliability becomes insufficient and faulty operation may occur in future before an objective product life expires. If a proper amount of time-varying degradation margin, which is one of design margins, cannot be determined, it becomes difficult to develop an LSI of which high performance and high reliability are required, such as a microprocessor.
Unlike an item, such as a microprocessor, for which a custom design scheme is used frequently, an application specific LSI such as ASIC is mostly designed by a labor-saving method using various delay varying factors termed derating factors, which are expressed as coefficients. In accordance with the method, design is performed by estimating a delay value under a worst condition from a standard delay value in a simple and easy manner, as represented by the following expression (3):t worst (Before Degradation)=t typ (Before Degradation)×P×V×T  (3)where t worst is a worst value of all signal path delays, t typ is a standard value of all the signal path delays before degradation, P is a delay varying coefficient due to manufacturing fluctuation, V is a delay varying coefficient due to a power-supply voltage range, and T is a delay varying coefficient due to a temperature range.
In this case, the standard value of all the signal path delays is obtained by simulation and the worst value is obtained by using, as a design margin, a value obtained by simply multiplying the standard value by the derating factors P, V, and T. The right side of the expression (3) corresponds to “Σti” in the expression (1).
In design performed by considering the time-varying degradation margin, a value obtained by newly adding, as a derating factor G, a permissible value of the degree of delay degradation of FIG. 11, i.e., the time-varying degradation margin to the expression (3) and multiplying the standard value by the derating factors P, V, T, and G is used as the design margin so that the delay value under the worst condition after degradation is calculated in a simple and easy manner from the standard delay value before degradation, as represented by the following expression (4):t worst (After Degradation)=t typ (Before Degradation)×P×V×T×G  (4).Design is performed such that the delay calculated in accordance with the expression (4) falls within the range of design objective delays. In that case, the expression (3) was used to obtain the delay value under the worst condition from the standard delay value before degradation.
However, the conventional reliability evaluation using the ring oscillator has the following problems.
Although the conventional reliability evaluation has performed measurement and evaluation by manufacturing a ring oscillator on a per generation basis, it requires an extremely large number of steps since, in normal process development, reliability should be performed repeatedly under different manufacturing conditions till a manufacturing condition is finally determined.
Although the conventional method has used the ring oscillator circuit composed of logic gates of one type, such as inverters, which are connected to each other as shown in FIG. 10, a circuit in an LSI is composed of logic circuits of different types so that the ring oscillator composed of logic gates of one type is not representative of the properties of the LSI. In accordance with the conventional method, therefore, it is difficult to perform the evaluation of reliability reflecting an actual LSI. For this reason, the conventional ring oscillator for reliability evaluation has been designed to have a large output load capacitance and a large input slope, which are conditions for accelerating degradation, so that the degree of degradation becomes higher than that of a circuit with a highest degree of degradation in the LSI. In the conventional design, therefore, an excessively strict standard should inevitably be provided for reliability evaluation. It is inevitable for the time-varying degradation margin and the derating factors to become excessively large because they were obtained as a result of reliability evaluation performed under excessively strict conditions. Thus, the use of the excessively large time-varying degradation margin and derating factors has rendered LSI design difficult and caused the problem of partially sacrificing the performance of the LSI.
It may be possible to perform evaluation by directly analyzing the reliabilities of LSIs on a per generation basis by simulation, instead of the foregoing reliability evaluation using the ring oscillator. However, simulation of each of the LSIs performed under each of process conditions on a per generation basis increases the number of steps and is therefore difficult. It may also be possible to perform evaluation by actually measuring LSIs manufactured by processes belonging to the same generation. However, it is not realistic in terms of time and the number of steps required for manufacturing and evaluation.